d-Matrix Unveils 100 TB/s Raptor 3D DRAM as 0.37 pJ/bit Challenges HBM4
Updated
Updated · Wccftech · Aug 24
d-Matrix Unveils 100 TB/s Raptor 3D DRAM as 0.37 pJ/bit Challenges HBM4
3 articles · Updated · Wccftech · Aug 24
Summary
Raptor pairs a TSMC 4nm logic die with custom 3D DRAM to deliver 32 GB and 100+ TB/s per card, which d-Matrix says targets the AI inference memory bottleneck.
At 0.37 pJ/bit, the design uses about one-tenth of HBM energy and avoids HBM’s PHY and beachfront limits, while pitch-matching 256 tensor engines to DRAM banks to cut data movement.
Against a 192 GB HBM4 setup at 18 TB/s and 2-3 pJ/bit, d-Matrix claims 5.6x higher bandwidth, 5-8x lower energy and 7x denser I/O; versus Nvidia’s Rubin R200 platform, it cites 23.4x higher bandwidth density.
The approach still faces thermal, power-delivery and yield hurdles: logic-on-top requires liquid cooling, I/O alone can draw about 300 W at 100 TB/s, and the DRAM refreshes every 4 ms with only 1.37% bandwidth loss.
Presented at Hot Chips 2026, Raptor extends d-Matrix’s push for an alternative to HBM as AI model sizes and KV-cache demands keep rising.