Updated

Updated · 매일경제 · Aug 23

SK Hynix Pushes 20-Layer HBM Packaging as AI Chip Design Shifts to 3D Co-Optimization

Updated

Updated · 매일경제 · Aug 23

SK Hynix Pushes 20-Layer HBM Packaging as AI Chip Design Shifts to 3D Co-Optimization

2 articles · Updated · 매일경제 · Aug 23

SK Hynix said HBM competition is moving from memory speed alone to packaging, with AI chips requiring memory, GPU, foundry and packaging teams to co-design from the start.
HBM now gets mounted first on the silicon interposer rather than late in system assembly, making reliability tougher because the memory must survive later heat and mechanical stress.
At Hot Chips 2026, the company detailed hybrid bonding for HBM stacks above 20 layers, saying it can raise core die thickness by up to 24% at the same height and cut bump spacing below 18 micrometers.
SK Hynix also outlined iHBM, which adds high-thermal-conductivity materials to cool hotspot areas created as HBM input/output speeds rise.
The presentation framed packaging’s path from 2D to 2.5D and then 3D, with heat, power and packaging emerging as the main constraints on future HBM bandwidth and capacity growth.

Sources

As SK Hynix pushes HBM4 to its thermal limits, will their radical 3D packaging revolution finally solve the AI memory bottleneck?

With memory and logic merging in custom base dies, is SK Hynix's hybrid bonding the ultimate weapon in the 2026 AI race?

Could the massive heat generated by next-gen 2TB/s memory stacks derail the entire semiconductor industry's transition to 3D integration?

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