D-Wave Demonstrates 500-ns Dual-Rail CZ Gate With 0.5% Erasure Rate

3 articles · Updated · Nature.com · Aug 5

A Nature paper reports D-Wave experimentally realized a two-qubit entangling gate for dual-rail cavity qubits that keeps the architecture’s error-detection advantages while operating in about 500 nanoseconds.
Benchmarking showed roughly 0.53% erasures per CZ gate, residual Pauli errors below 0.1%, and bit-flip errors near 10^-6, with Bell-state fidelity reaching 99.60% after post-selection.
The gate’s errors were strongly structured rather than uniform: control-qubit erasures were about 0.400% per gate versus 0.096% on the target, and dephasing dominated over bit flips.
Leakage before or during the gate largely produced benign behavior—either effectively skipping later CZ action or causing conditional dephasing—making delayed erasure checks more practical for error correction.
Surface-code simulations cited in the study suggest current performance is already about 10 times below relevant erasure and dephasing thresholds, pointing to faster scaling toward fault-tolerant quantum computing.

Sources

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Nature.com1d ago

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D-Wave’s Dual-Platform Quantum Leap: The Path to 100 Logical Qubits and Commercial Fault Tolerance

Overview

D-Wave Quantum’s 2026 acquisition of Quantum Circuits, Inc. brought proprietary dual-rail superconducting qubit technology, enabling D-Wave to offer both quantum annealing and gate-model quantum computing systems. This integration positioned D-Wave to address the full quantum market and fueled rapid financial growth, with major deals and a surge in bookings. The dual-rail design embeds real-time error detection, allowing logical qubits to be created with far fewer physical qubits. D-Wave’s roadmap aims for a 100-logical-qubit system by 2032, promising breakthroughs in molecular R&D and materials science, while enterprises prepare by adopting quantum workflows today.

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